High-level driver for communication between CPU and LAN9211 in an IP-Manager-based environment.
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#define | MAC_TIMEOUT 200 |
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#define | PHY_TIMEOUT 200 |
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#define | FALSE 0 |
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#define | TRUE 1 |
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#define | RX_FIFO_PORT (uint16_t)(0x00) |
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#define | RX_FIFO_ALIAS_PORTS (uint16_t)(0x4) |
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#define | TX_FIFO_PORT (uint16_t)(0x20) |
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#define | TX_FIFO_ALIAS_PORTS (uint16_t)(0x24) |
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#define | RX_STATUS_FIFO_PORT (uint16_t)(0x40) |
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#define | RX_STATUS_FIFO_PEEK (uint16_t)(0x44) |
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#define | TX_STATUS_FIFO_PORT (uint16_t)(0x48) |
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#define | TX_STATUS_FIFO_PEEK (uint16_t)(0x4C) |
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#define | TX_STATUS_FIFO_ES (uint16_t)(0x8000) |
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#define | TX_STATUS_FIFO_TAG_MSK (uint16_t)(0xffff0000) |
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#define | ID_REV (uint16_t)(0x50) |
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#define | ID_REV_ID_MASK (0xFFFF0000) |
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#define | ID_REV_REV_MASK (0x0000FFFF) |
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#define | IRQ_CFG (uint16_t)(0x54) |
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#define | IRQ_CFG_MASTER_INT (0x00001000) |
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#define | IRQ_CFG_ENABLE (0x00000100) |
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#define | IRQ_CFG_IRQ_POL_HIGH (0x00000010) |
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#define | IRQ_CFG_IRQ_TYPE_PUPU (0x00000001) |
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#define | INT_STS (uint16_t)(0x58) |
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#define | INT_STS_SW_INT (0x80000000) |
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#define | INT_STS_TXSTOP_INT (0x02000000) |
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#define | INT_STS_RXSTOP_INT (0x01000000) |
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#define | INT_STS_RXDFH_INT (0x00800000) |
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#define | INT_STS_TIOC_INT (0x00200000) |
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#define | INT_STS_GPT_INT (0x00080000) |
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#define | INT_STS_PHY_INT (0x00040000) |
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#define | INT_STS_PMT_INT (0x00020000) |
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#define | INT_STS_TXSO_INT (0x00010000) |
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#define | INT_STS_RWT_INT (0x00008000) |
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#define | INT_STS_RXE_INT (0x00004000) |
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#define | INT_STS_TXE_INT (0x00002000) |
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#define | INT_STS_TDFO_INT (0x00000400) |
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#define | INT_STS_TDFA_INT (0x00000200) |
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#define | INT_STS_TSFF_INT (0x00000100) |
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#define | INT_STS_TSFL_INT (0x00000080) |
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#define | INT_STS_RDFO_INT (0x00000040) |
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#define | INT_STS_RSFF_INT (0x00000010) |
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#define | INT_STS_RSFL_INT (0x00000008) |
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#define | INT_STS_GPIO2_INT (0x00000004) |
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#define | INT_STS_GPIO1_INT (0x00000002) |
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#define | INT_STS_GPIO0_INT (0x00000001) |
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#define | INT_EN (uint16_t)(0x5C) |
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#define | INT_EN_SW_INT_EN (0x80000000) |
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#define | INT_EN_TXSTOP_INT_EN (0x02000000) |
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#define | INT_EN_RXSTOP_INT_EN (0x01000000) |
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#define | INT_EN_RXDFH_INT_EN (0x00800000) |
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#define | INT_EN_TIOC_INT_EN (0x00200000) |
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#define | INT_EN_GPT_INT_EN (0x00080000) |
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#define | INT_EN_PHY_INT_EN (0x00040000) |
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#define | INT_EN_PMT_INT_EN (0x00020000) |
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#define | INT_EN_TXSO_INT_EN (0x00010000) |
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#define | INT_EN_RWT_INT_EN (0x00008000) |
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#define | INT_EN_RXE_INT_EN (0x00004000) |
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#define | INT_EN_TXE_INT_EN (0x00002000) |
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#define | INT_EN_TDFO_INT_EN (0x00000400) |
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#define | INT_EN_TDFA_INT_EN (0x00000200) |
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#define | INT_EN_TSFF_INT_EN (0x00000100) |
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#define | INT_EN_TSFL_INT_EN (0x00000080) |
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#define | INT_EN_RDFO_INT_EN (0x00000040) |
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#define | INT_EN_RSFF_INT_EN (0x00000010) |
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#define | INT_EN_RSFL_INT_EN (0x00000008) |
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#define | INT_EN_GPIO2_EN (0x00000004) |
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#define | INT_EN_GPIO1_EN (0x00000002) |
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#define | INT_EN_GPIO0_EN (0x00000001) |
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#define | BYTE_TEST (uint16_t)(0x64) |
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#define | BYTE_TEST_VAL (0x87654321) |
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#define | FIFO_INT (uint16_t)(0x68) |
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#define | FIFO_INT_TDAL_MSK (0xFF000000) |
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#define | FIFO_INT_TSL_MSK (0x00FF0000) |
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#define | FIFO_INT_RSL_MSK (0x000000FF) |
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#define | RX_CFG (uint16_t)(0x6C) |
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#define | RX_CFG_END_ALIGN4 (0x00000000) |
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#define | RX_CFG_END_ALIGN16 (0x40000000) |
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#define | RX_CFG_END_ALIGN32 (0x80000000) |
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#define | RX_CFG_FORCE_DISCARD (0x00008000) |
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#define | RX_CFG_RXDOFF_MSK (0x00003C00) |
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#define | TX_CFG (uint16_t)(0x70) |
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#define | TX_CFG_TXS_DUMP (0x00008000) |
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#define | TX_CFG_TXD_DUMP (0x00004000) |
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#define | TX_CFG_TXSAO (0x00000004) |
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#define | TX_CFG_TX_ON (0x00000002) |
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#define | TX_CFG_STOP_TX (0x00000001) |
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#define | HW_CFG (uint16_t)(0x74) |
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#define | HW_CFG_MBO (0x00100000) |
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#define | HW_CFG_TX_FIF_SZ_MSK (0x000F0000) |
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#define | HW_CFG_BITMD_MSK (0x00000004) |
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#define | HW_CFG_BITMD_32 (0x00000004) |
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#define | HW_CFG_SRST_TO (0x00000002) |
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#define | HW_CFG_SRST (0x00000001) |
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#define | RX_DP_CTL (uint16_t)(0x78) |
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#define | RX_DP_FFWD (0x80000000) |
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#define | RX_FIFO_INF (uint16_t)(0x7C) |
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#define | RX_FIFO_RXSUSED_MSK (0x00FF0000) |
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#define | RX_FIFO_RXDUSED_MSK (0x0000FFFF) |
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#define | TX_FIFO_INF (uint16_t)(0x80) |
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#define | TX_FIFO_TXSUSED_MSK (0x00FF0000) |
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#define | TX_FIFO_TDFREE_MSK (0x0000FFFF) |
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#define | PWR_MGMT (uint16_t)(0x84) |
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#define | PWR_MGMT_PM_MODE_MSK (0x00003000) |
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#define | PWR_MGMT_PM_MODE_MSK_LE (0x00000003) |
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#define | PWR_MGMT_PM__D0 (0x00000000) |
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#define | PWR_MGMT_PM__D1 (0x00010000) |
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#define | PWR_MGMT_PM__D2 (0x00020000) |
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#define | PWR_MGMT_PHY_RST (0x00000400) |
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#define | PWR_MGMT_WOL_EN (0x00000200) |
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#define | PWR_MGMT_ED_EN (0x00000100) |
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#define | PWR_MGMT_PME_TYPE_PUPU (0x00000040) |
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#define | PWR_MGMT_WUPS_MSK (0x00000030) |
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#define | PWR_MGMT_WUPS_NOWU (0x00000000) |
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#define | PWR_MGMT_WUPS_D2D0 (0x00000010) |
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#define | PWR_MGMT_WUPS_D1D0 (0x00000020) |
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#define | PWR_MGMT_WUPS_UNDEF (0x00000030) |
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#define | PWR_MGMT_PME_IND_PUL (0x00000008) |
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#define | PWR_MGMT_PME_POL_HIGH (0x00000004) |
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#define | PWR_MGMT_PME_EN (0x00000002) |
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#define | PWR_MGMT_PME_READY (0x00000001) |
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#define | GPIO_CFG (uint16_t)(0x88) |
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#define | GPIO_CFG_LEDx_MSK (0x70000000) |
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#define | GPIO_CFG_LED1_EN (0x10000000) |
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#define | GPIO_CFG_LED2_EN (0x20000000) |
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#define | GPIO_CFG_LED3_EN (0x40000000) |
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#define | GPIO_CFG_GPIOBUFn_MSK (0x00070000) |
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#define | GPIO_CFG_GPIOBUF0_PUPU (0x00010000) |
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#define | GPIO_CFG_GPIOBUF1_PUPU (0x00020000) |
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#define | GPIO_CFG_GPIOBUF2_PUPU (0x00040000) |
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#define | GPIO_CFG_GPDIRn_MSK (0x00000700) |
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#define | GPIO_CFG_GPIOBUF0_OUT (0x00000100) |
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#define | GPIO_CFG_GPIOBUF1_OUT (0x00000200) |
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#define | GPIO_CFG_GPIOBUF2_OUT (0x00000400) |
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#define | GPIO_CFG_GPIOD_MSK (0x00000007) |
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#define | GPIO_CFG_GPIOD0 (0x00000001) |
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#define | GPIO_CFG_GPIOD1 (0x00000002) |
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#define | GPIO_CFG_GPIOD2 (0x00000004) |
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#define | GPT_CFG (uint16_t)(0x8C) |
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#define | GPT_CFG_TIMER_EN (0x20000000) |
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#define | GPT_CFG_GPT_LOAD_MSK (0x0000FFFF) |
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#define | GPT_CNT (uint16_t)(0x90) |
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#define | GPT_CNT_MSK (0x0000FFFF) |
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#define | FPGA_REV (uint16_t)(0x94) |
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#define | ENDIAN (uint16_t)(0x98) |
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#define | ENDIAN_BIG (0xFFFFFFFF) |
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#define | FREE_RUN (uint16_t)(0x9C) |
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#define | FREE_RUN_FR_CNT_MSK (0xFFFFFFFF) |
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#define | RX_DROP (uint16_t)(0xA0) |
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#define | RX_DROP_RX_DFC_MSK (0xFFFFFFFF) |
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#define | MAC_CSR_CMD (uint16_t)(0xA4) |
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#define | MAC_CSR_CMD_CSR_BUSY (0x80000000) |
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#define | MAC_CSR_CMD_RNW (0x40000000) |
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#define | MAC_RD_CMD(Reg) |
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#define | MAC_WR_CMD(Reg) |
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#define | MAC_CSR_DATA (uint16_t)(0xA8) |
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#define | AFC_CFG (uint16_t)(0xAC) |
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#define | AFC_CFG_AFC_HI_MSK (0x00FF0000) |
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#define | AFC_CFG_AFC_LO_MSK (0x0000FF00) |
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#define | E2P_CMD (uint16_t)(0xB0) |
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#define | E2P_DATA (uint16_t)(0xB4) |
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#define | MAC_CR (uint16_t)(0x01) |
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#define | MAC_CR_RXALL (0x80000000) |
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#define | MAC_CR_HBDIS (0x10000000) |
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#define | MAC_CR_RCVOWN (0x00800000) |
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#define | MAC_CR_LOOPBK (0x00200000) |
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#define | MAC_CR_FDPX (0x00100000) |
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#define | MAC_CR_MCPAS (0x00080000) |
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#define | MAC_CR_PRMS (0x00040000) |
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#define | MAC_CR_INVFILT (0x00020000) |
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#define | MAC_CR_PASSBAD (0x00010000) |
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#define | MAC_CR_HFILT (0x00008000) |
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#define | MAC_CR_HPFILT (0x00002000) |
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#define | MAC_CR_LCOLL (0x00001000) |
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#define | MAC_CR_BCAST (0x00000800) |
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#define | MAC_CR_DISRTY (0x00000400) |
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#define | MAC_CR_PADSTR (0x00000100) |
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#define | MAC_CR_BOLMT_MSK (0x000000C0) |
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#define | MAC_CR_BOLMT_10 (0x00000000) |
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#define | MAC_CR_BOLMT_8 (0x00000040) |
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#define | MAC_CR_BOLMT_4 (0x00000080) |
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#define | MAC_CR_BOLMT_1 (0x000000C0) |
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#define | MAC_CR_DFCHK (0x00000020) |
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#define | MAC_CR_TXEN (0x00000008) |
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#define | MAC_CR_RXEN (0x00000004) |
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#define | MAC_ADDRH (uint16_t)(0x02) |
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#define | MAC_ADDRH_MSK (0x0000FFFF) |
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#define | MAC_ADDRL (uint16_t)(0x03) |
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#define | MAC_ADDRL_MSK (0xFFFFFFFF) |
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#define | MAC_HASHH (uint16_t)(0x04) |
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#define | MAC_HASHH_MSK (0xFFFFFFFF) |
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#define | MAC_HASHL (uint16_t)(0x05) |
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#define | MAC_HASHL_MSK (0xFFFFFFFF) |
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#define | MAC_MIIACC (uint16_t)(0x06) |
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#define | MAC_MIIACC_MII_WRITE (0x00000002) |
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#define | MAC_MIIACC_MII_BUSY (0x00000001) |
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#define | MAC_MII_RD_CMD(Addr, Reg) |
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#define | MAC_MII_WR_CMD(Addr, Reg) |
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#define | MAC_MIIDATA (uint16_t)(0x07) |
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#define | MAC_MIIDATA_MSK (0x0000FFFF) |
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#define | MAC_MII_DATA(Data) (Data & MAC_MIIDATA_MSK) |
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#define | MAC_FLOW (uint16_t)(0x08) |
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#define | MAC_FLOW_FCPT_MSK (0xFFFF0000) |
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#define | MAC_FLOW_FCPASS (0x00000004) |
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#define | MAC_FLOW_FCEN (0x00000002) |
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#define | MAC_FLOW_FCBSY (0x00000001) |
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#define | MAC_VLAN1 (uint16_t)(0x09) |
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#define | MAC_VLAN2 (uint16_t)(0x0A) |
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#define | MAC_WUFF (uint16_t)(0x0B) |
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#define | MAC_WUCSR (uint16_t)(0x0C) |
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#define | MAC_WUCSR_GUE (0x00000200) |
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#define | MAC_WUCSR_WUFR (0x00000040) |
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#define | MAC_WUCSR_MPR (0x00000020) |
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#define | MAC_WUCSR_WUEN (0x00000004) |
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#define | MAC_WUCSR_MPEN (0x00000002) |
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#define | MAC_COE_CR (uint16_t)(0x0D) |
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#define | MAC_COE_CR_TXCOE_EN (0x00010000) |
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#define | MAC_COE_CR_RXCOE_MODE (0x00000002) |
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#define | MAC_COE_CR_RXCOE_EN (0x00000001) |
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#define | PHY_BCR (uint16_t)(0x00) |
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#define | PHY_BCR_RST (0x8000) |
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#define | PHY_BCR_LOOPBK (0x4000) |
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#define | PHY_BCR_SS (0x2000) |
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#define | PHY_BCR_ANE (0x1000) |
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#define | PHY_BCR_PWRDN (0x0800) |
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#define | PHY_BCR_RSTAN (0x0200) |
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#define | PHY_BCR_FDPLX (0x0100) |
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#define | PHY_BCR_COLLTST (0x0080) |
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#define | PHY_BSR (uint16_t)(0x01) |
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#define | PHY_BSR_100_T4_ABLE (0x8000) |
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#define | PHY_BSR_100_TX_FDPLX (0x4000) |
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#define | PHY_BSR_100_TX_HDPLX (0x2000) |
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#define | PHY_BSR_10_FDPLX (0x1000) |
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#define | PHY_BSR_10_HDPLX (0x0800) |
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#define | PHY_BSR_ANC (0x0020) |
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#define | PHY_BSR_REM_FAULT (0x0010) |
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#define | PHY_BSR_AN_ABLE (0x0008) |
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#define | PHY_BSR_LINK_STATUS (0x0004) |
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#define | PHY_BSR_JAB_DET (0x0002) |
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#define | PHY_BSR_EXT_CAP (0x0001) |
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#define | PHY_ID1 (uint16_t)(0x02) |
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#define | PHY_ID1_MSK (0xFFFF) |
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#define | PHY_ID1_LAN9118 (0x0007) |
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#define | PHY_ID1_LAN9218 (PHY_ID1_LAN9118) |
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#define | PHY_ID2 (uint16_t)(0x03) |
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#define | PHY_ID2_MSK (0xFFFF) |
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#define | PHY_ID2_MODEL_MSK (0x03F0) |
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#define | PHY_ID2_REV_MSK (0x000F) |
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#define | PHY_ID2_LAN9118 (0xC0D1) |
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#define | PHY_ID2_LAN9218 (0xC0C3) |
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#define | PHY_ANAR (uint16_t)(0x04) |
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#define | PHY_ANAR_NXTPG_CAP (0x8000) |
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#define | PHY_ANAR_REM_FAULT (0x2000) |
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#define | PHY_ANAR_PAUSE_OP_MSK (0x0C00) |
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#define | PHY_ANAR_PAUSE_OP_NONE (0x0000) |
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#define | PHY_ANAR_PAUSE_OP_ASLP (0x0400) |
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#define | PHY_ANAR_PAUSE_OP_SLP (0x0800) |
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#define | PHY_ANAR_PAUSE_OP_BOTH (0x0C00) |
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#define | PHY_ANAR_100_T4_ABLE (0x0200) |
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#define | PHY_ANAR_100_TX_FDPLX (0x0100) |
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#define | PHY_ANAR_100_TX_ABLE (0x0080) |
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#define | PHY_ANAR_10_FDPLX (0x0040) |
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#define | PHY_ANAR_10_ABLE (0x0020) |
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#define | PHY_ANLPAR (uint16_t)(0x05) |
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#define | PHY_ANLPAR_NXTPG_CAP (0x8000) |
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#define | PHY_ANLPAR_ACK (0x4000) |
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#define | PHY_ANLPAR_REM_FAULT (0x2000) |
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#define | PHY_ANLPAR_PAUSE_CAP (0x0400) |
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#define | PHY_ANLPAR_100_T4_ABLE (0x0200) |
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#define | PHY_ANLPAR_100_TX_FDPLX (0x0100) |
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#define | PHY_ANLPAR_100_TX_ABLE (0x0080) |
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#define | PHY_ANLPAR_10_FDPLX (0x0040) |
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#define | PHY_ANLPAR_10_ABLE (0x0020) |
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#define | PHY_ANEXPR (uint16_t)(0x06) |
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#define | PHY_ANEXPR_PARDET_FAULT (0x0010) |
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#define | PHY_ANEXPR_LP_NXTPG_CAP (0x0008) |
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#define | PHY_ANEXPR_NXTPG_CAP (0x0004) |
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#define | PHY_ANEXPR_NEWPG_REC (0x0002) |
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#define | PHY_ANEXPR_LP_AN_ABLE (0x0001) |
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#define | PHY_MCSR (uint16_t)(0x11) |
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#define | PHY_MCSR_EDPWRDOWN (0x2000) |
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#define | PHY_MCSR_ENERGYON (0x0002) |
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#define | PHY_SPMODES (uint16_t)(0x12) |
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#define | PHY_CSIR (uint16_t)(0x1B) |
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#define | PHY_CSIR_SQEOFF (0x0800) |
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#define | PHY_CSIR_FEFIEN (0x0020) |
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#define | PHY_CSIR_XPOL (0x0010) |
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#define | PHY_ISR (uint16_t)(0x1D) |
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#define | PHY_ISR_INT7 (0x0080) |
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#define | PHY_ISR_INT6 (0x0040) |
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#define | PHY_ISR_INT5 (0x0020) |
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#define | PHY_ISR_INT4 (0x0010) |
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#define | PHY_ISR_INT3 (0x0008) |
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#define | PHY_ISR_INT2 (0x0004) |
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#define | PHY_ISR_INT1 (0x0002) |
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#define | PHY_IMR (uint16_t)(0x1E) |
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#define | PHY_IMR_INT7 (0x0080) |
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#define | PHY_IMR_INT6 (0x0040) |
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#define | PHY_IMR_INT5 (0x0020) |
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#define | PHY_IMR_INT4 (0x0010) |
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#define | PHY_IMR_INT3 (0x0008) |
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#define | PHY_IMR_INT2 (0x0004) |
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#define | PHY_IMR_INT1 (0x0002) |
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#define | PHY_PHYSCSR (uint16_t)(0x1F) |
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#define | PHY_PHYSCSR_ANDONE (0x1000) |
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#define | PHY_PHYSCSR_4B5B_EN (0x0040) |
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#define | PHY_PHYSCSR_SPEED_MSK (0x001C) |
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#define | PHY_PHYSCSR_SPEED_10HD (0x0004) |
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#define | PHY_PHYSCSR_SPEED_10FD (0x0014) |
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#define | PHY_PHYSCSR_SPEED_100HD (0x0008) |
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#define | PHY_PHYSCSR_SPEED_100FD (0x0018) |
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