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#define | RX_FIFO_PORT (uint16_t)(0x00) |
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#define | RX_FIFO_ALIAS_PORTS (uint16_t)(0x4) |
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#define | TX_FIFO_PORT (uint16_t)(0x20) |
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#define | TX_FIFO_ALIAS_PORTS (uint16_t)(0x24) |
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#define | RX_STATUS_FIFO_PORT (uint16_t)(0x40) |
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#define | RX_STATUS_FIFO_PEEK (uint16_t)(0x44) |
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#define | TX_STATUS_FIFO_PORT (uint16_t)(0x48) |
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#define | TX_STATUS_FIFO_PEEK (uint16_t)(0x4C) |
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#define | TX_STATUS_FIFO_ES (uint16_t)(0x8000) |
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#define | TX_STATUS_FIFO_TAG_MSK (uint16_t)(0xffff0000) |
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#define | ID_REV (uint16_t)(0x50) |
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#define | ID_REV_ID_MASK (0xFFFF0000) |
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#define | ID_REV_REV_MASK (0x0000FFFF) |
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#define | IRQ_CFG (uint16_t)(0x54) |
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#define | IRQ_CFG_MASTER_INT (0x00001000) |
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#define | IRQ_CFG_ENABLE (0x00000100) |
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#define | IRQ_CFG_IRQ_POL_HIGH (0x00000010) |
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#define | IRQ_CFG_IRQ_TYPE_PUPU (0x00000001) |
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#define | INT_STS (uint16_t)(0x58) |
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#define | INT_STS_SW_INT (0x80000000) |
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#define | INT_STS_TXSTOP_INT (0x02000000) |
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#define | INT_STS_RXSTOP_INT (0x01000000) |
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#define | INT_STS_RXDFH_INT (0x00800000) |
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#define | INT_STS_TIOC_INT (0x00200000) |
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#define | INT_STS_GPT_INT (0x00080000) |
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#define | INT_STS_PHY_INT (0x00040000) |
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#define | INT_STS_PMT_INT (0x00020000) |
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#define | INT_STS_TXSO_INT (0x00010000) |
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#define | INT_STS_RWT_INT (0x00008000) |
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#define | INT_STS_RXE_INT (0x00004000) |
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#define | INT_STS_TXE_INT (0x00002000) |
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#define | INT_STS_TDFO_INT (0x00000400) |
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#define | INT_STS_TDFA_INT (0x00000200) |
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#define | INT_STS_TSFF_INT (0x00000100) |
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#define | INT_STS_TSFL_INT (0x00000080) |
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#define | INT_STS_RDFO_INT (0x00000040) |
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#define | INT_STS_RSFF_INT (0x00000010) |
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#define | INT_STS_RSFL_INT (0x00000008) |
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#define | INT_STS_GPIO2_INT (0x00000004) |
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#define | INT_STS_GPIO1_INT (0x00000002) |
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#define | INT_STS_GPIO0_INT (0x00000001) |
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#define | INT_EN (uint16_t)(0x5C) |
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#define | INT_EN_SW_INT_EN (0x80000000) |
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#define | INT_EN_TXSTOP_INT_EN (0x02000000) |
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#define | INT_EN_RXSTOP_INT_EN (0x01000000) |
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#define | INT_EN_RXDFH_INT_EN (0x00800000) |
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#define | INT_EN_TIOC_INT_EN (0x00200000) |
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#define | INT_EN_GPT_INT_EN (0x00080000) |
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#define | INT_EN_PHY_INT_EN (0x00040000) |
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#define | INT_EN_PMT_INT_EN (0x00020000) |
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#define | INT_EN_TXSO_INT_EN (0x00010000) |
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#define | INT_EN_RWT_INT_EN (0x00008000) |
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#define | INT_EN_RXE_INT_EN (0x00004000) |
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#define | INT_EN_TXE_INT_EN (0x00002000) |
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#define | INT_EN_TDFO_INT_EN (0x00000400) |
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#define | INT_EN_TDFA_INT_EN (0x00000200) |
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#define | INT_EN_TSFF_INT_EN (0x00000100) |
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#define | INT_EN_TSFL_INT_EN (0x00000080) |
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#define | INT_EN_RDFO_INT_EN (0x00000040) |
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#define | INT_EN_RSFF_INT_EN (0x00000010) |
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#define | INT_EN_RSFL_INT_EN (0x00000008) |
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#define | INT_EN_GPIO2_EN (0x00000004) |
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#define | INT_EN_GPIO1_EN (0x00000002) |
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#define | INT_EN_GPIO0_EN (0x00000001) |
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#define | BYTE_TEST (uint16_t)(0x64) |
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#define | BYTE_TEST_VAL (0x87654321) |
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#define | FIFO_INT (uint16_t)(0x68) |
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#define | FIFO_INT_TDAL_MSK (0xFF000000) |
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#define | FIFO_INT_TSL_MSK (0x00FF0000) |
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#define | FIFO_INT_RSL_MSK (0x000000FF) |
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#define | RX_CFG (uint16_t)(0x6C) |
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#define | RX_CFG_END_ALIGN4 (0x00000000) |
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#define | RX_CFG_END_ALIGN16 (0x40000000) |
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#define | RX_CFG_END_ALIGN32 (0x80000000) |
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#define | RX_CFG_FORCE_DISCARD (0x00008000) |
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#define | RX_CFG_RXDOFF_MSK (0x00003C00) |
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#define | TX_CFG (uint16_t)(0x70) |
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#define | TX_CFG_TXS_DUMP (0x00008000) |
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#define | TX_CFG_TXD_DUMP (0x00004000) |
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#define | TX_CFG_TXSAO (0x00000004) |
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#define | TX_CFG_TX_ON (0x00000002) |
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#define | TX_CFG_STOP_TX (0x00000001) |
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#define | HW_CFG (uint16_t)(0x74) |
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#define | HW_CFG_MBO (0x00100000) |
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#define | HW_CFG_TX_FIF_SZ_MSK (0x000F0000) |
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#define | HW_CFG_BITMD_MSK (0x00000004) |
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#define | HW_CFG_BITMD_32 (0x00000004) |
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#define | HW_CFG_SRST_TO (0x00000002) |
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#define | HW_CFG_SRST (0x00000001) |
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#define | RX_DP_CTL (uint16_t)(0x78) |
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#define | RX_DP_FFWD (0x80000000) |
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#define | RX_FIFO_INF (uint16_t)(0x7C) |
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#define | RX_FIFO_RXSUSED_MSK (0x00FF0000) |
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#define | RX_FIFO_RXDUSED_MSK (0x0000FFFF) |
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#define | TX_FIFO_INF (uint16_t)(0x80) |
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#define | TX_FIFO_TXSUSED_MSK (0x00FF0000) |
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#define | TX_FIFO_TDFREE_MSK (0x0000FFFF) |
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#define | PWR_MGMT (uint16_t)(0x84) |
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#define | PWR_MGMT_PM_MODE_MSK (0x00003000) |
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#define | PWR_MGMT_PM_MODE_MSK_LE (0x00000003) |
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#define | PWR_MGMT_PM__D0 (0x00000000) |
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#define | PWR_MGMT_PM__D1 (0x00010000) |
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#define | PWR_MGMT_PM__D2 (0x00020000) |
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#define | PWR_MGMT_PHY_RST (0x00000400) |
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#define | PWR_MGMT_WOL_EN (0x00000200) |
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#define | PWR_MGMT_ED_EN (0x00000100) |
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#define | PWR_MGMT_PME_TYPE_PUPU (0x00000040) |
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#define | PWR_MGMT_WUPS_MSK (0x00000030) |
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#define | PWR_MGMT_WUPS_NOWU (0x00000000) |
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#define | PWR_MGMT_WUPS_D2D0 (0x00000010) |
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#define | PWR_MGMT_WUPS_D1D0 (0x00000020) |
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#define | PWR_MGMT_WUPS_UNDEF (0x00000030) |
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#define | PWR_MGMT_PME_IND_PUL (0x00000008) |
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#define | PWR_MGMT_PME_POL_HIGH (0x00000004) |
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#define | PWR_MGMT_PME_EN (0x00000002) |
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#define | PWR_MGMT_PME_READY (0x00000001) |
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#define | GPIO_CFG (uint16_t)(0x88) |
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#define | GPIO_CFG_LEDx_MSK (0x70000000) |
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#define | GPIO_CFG_LED1_EN (0x10000000) |
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#define | GPIO_CFG_LED2_EN (0x20000000) |
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#define | GPIO_CFG_LED3_EN (0x40000000) |
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#define | GPIO_CFG_GPIOBUFn_MSK (0x00070000) |
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#define | GPIO_CFG_GPIOBUF0_PUPU (0x00010000) |
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#define | GPIO_CFG_GPIOBUF1_PUPU (0x00020000) |
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#define | GPIO_CFG_GPIOBUF2_PUPU (0x00040000) |
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#define | GPIO_CFG_GPDIRn_MSK (0x00000700) |
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#define | GPIO_CFG_GPIOBUF0_OUT (0x00000100) |
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#define | GPIO_CFG_GPIOBUF1_OUT (0x00000200) |
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#define | GPIO_CFG_GPIOBUF2_OUT (0x00000400) |
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#define | GPIO_CFG_GPIOD_MSK (0x00000007) |
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#define | GPIO_CFG_GPIOD0 (0x00000001) |
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#define | GPIO_CFG_GPIOD1 (0x00000002) |
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#define | GPIO_CFG_GPIOD2 (0x00000004) |
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#define | GPT_CFG (uint16_t)(0x8C) |
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#define | GPT_CFG_TIMER_EN (0x20000000) |
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#define | GPT_CFG_GPT_LOAD_MSK (0x0000FFFF) |
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#define | GPT_CNT (uint16_t)(0x90) |
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#define | GPT_CNT_MSK (0x0000FFFF) |
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#define | FPGA_REV (uint16_t)(0x94) |
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#define | ENDIAN (uint16_t)(0x98) |
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#define | ENDIAN_BIG (0xFFFFFFFF) |
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#define | FREE_RUN (uint16_t)(0x9C) |
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#define | FREE_RUN_FR_CNT_MSK (0xFFFFFFFF) |
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#define | RX_DROP (uint16_t)(0xA0) |
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#define | RX_DROP_RX_DFC_MSK (0xFFFFFFFF) |
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#define | MAC_CSR_CMD (uint16_t)(0xA4) |
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#define | MAC_CSR_CMD_CSR_BUSY (0x80000000) |
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#define | MAC_CSR_CMD_RNW (0x40000000) |
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#define | MAC_RD_CMD(Reg) |
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#define | MAC_WR_CMD(Reg) |
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#define | MAC_CSR_DATA (uint16_t)(0xA8) |
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#define | AFC_CFG (uint16_t)(0xAC) |
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#define | AFC_CFG_AFC_HI_MSK (0x00FF0000) |
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#define | AFC_CFG_AFC_LO_MSK (0x0000FF00) |
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#define | E2P_CMD (uint16_t)(0xB0) |
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#define | E2P_DATA (uint16_t)(0xB4) |
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