ETHERNET SMART BRIDGE
Alberto Carboni, Alessio CiarciĆ , Jacopo Grecuccio, Lorenzo Zaia
lan9211.h
Go to the documentation of this file.
1 
6 #ifndef SMSC9211_H
7 #define SMSC9211_H
8 
9 #include "inttypes.h"
10 #include "string.h"
11 
12 /**** DEFINITIONS ****/
13 #define MAC_TIMEOUT 200
14 #define PHY_TIMEOUT 200
15 #define FALSE 0
16 #define TRUE 1
17 
18 
19 /******************************************************************************
20  * LAN9211 MEMORY MAP
21  ******************************************************************************/
22 /**** MAC CONTROL/STATUS REGISTERS (directly addressable registers) ****/
27 #define RX_FIFO_PORT (uint16_t)(0x00)
29 #define RX_FIFO_ALIAS_PORTS (uint16_t)(0x4)
30 #define TX_FIFO_PORT (uint16_t)(0x20)
31 #define TX_FIFO_ALIAS_PORTS (uint16_t)(0x24)
32 #define RX_STATUS_FIFO_PORT (uint16_t)(0x40)
33 #define RX_STATUS_FIFO_PEEK (uint16_t)(0x44)
34 #define TX_STATUS_FIFO_PORT (uint16_t)(0x48)
35 #define TX_STATUS_FIFO_PEEK (uint16_t)(0x4C)
36 #define TX_STATUS_FIFO_ES (uint16_t)(0x8000)
37 #define TX_STATUS_FIFO_TAG_MSK (uint16_t)(0xffff0000)
38 
39 #define ID_REV (uint16_t)(0x50)
40 #define ID_REV_ID_MASK (0xFFFF0000)
41 #define ID_REV_REV_MASK (0x0000FFFF)
42 
43 #define IRQ_CFG (uint16_t)(0x54)
44 #define IRQ_CFG_MASTER_INT (0x00001000)
45 #define IRQ_CFG_ENABLE (0x00000100)
46 #define IRQ_CFG_IRQ_POL_HIGH (0x00000010)
47 #define IRQ_CFG_IRQ_TYPE_PUPU (0x00000001)
48 
49 #define INT_STS (uint16_t)(0x58)
50 #define INT_STS_SW_INT (0x80000000)
51 #define INT_STS_TXSTOP_INT (0x02000000)
52 #define INT_STS_RXSTOP_INT (0x01000000)
53 #define INT_STS_RXDFH_INT (0x00800000)
54 #define INT_STS_TIOC_INT (0x00200000)
55 #define INT_STS_GPT_INT (0x00080000)
56 #define INT_STS_PHY_INT (0x00040000)
57 #define INT_STS_PMT_INT (0x00020000)
58 #define INT_STS_TXSO_INT (0x00010000)
59 #define INT_STS_RWT_INT (0x00008000)
60 #define INT_STS_RXE_INT (0x00004000)
61 #define INT_STS_TXE_INT (0x00002000)
62 #define INT_STS_TDFO_INT (0x00000400)
63 #define INT_STS_TDFA_INT (0x00000200)
64 #define INT_STS_TSFF_INT (0x00000100)
65 #define INT_STS_TSFL_INT (0x00000080)
66 #define INT_STS_RDFO_INT (0x00000040)
67 #define INT_STS_RSFF_INT (0x00000010)
68 #define INT_STS_RSFL_INT (0x00000008)
69 #define INT_STS_GPIO2_INT (0x00000004)
70 #define INT_STS_GPIO1_INT (0x00000002)
71 #define INT_STS_GPIO0_INT (0x00000001)
72 
73 #define INT_EN (uint16_t)(0x5C)
74 #define INT_EN_SW_INT_EN (0x80000000)
75 #define INT_EN_TXSTOP_INT_EN (0x02000000)
76 #define INT_EN_RXSTOP_INT_EN (0x01000000)
77 #define INT_EN_RXDFH_INT_EN (0x00800000)
78 #define INT_EN_TIOC_INT_EN (0x00200000)
79 #define INT_EN_GPT_INT_EN (0x00080000)
80 #define INT_EN_PHY_INT_EN (0x00040000)
81 #define INT_EN_PMT_INT_EN (0x00020000)
82 #define INT_EN_TXSO_INT_EN (0x00010000)
83 #define INT_EN_RWT_INT_EN (0x00008000)
84 #define INT_EN_RXE_INT_EN (0x00004000)
85 #define INT_EN_TXE_INT_EN (0x00002000)
86 #define INT_EN_TDFO_INT_EN (0x00000400)
87 #define INT_EN_TDFA_INT_EN (0x00000200)
88 #define INT_EN_TSFF_INT_EN (0x00000100)
89 #define INT_EN_TSFL_INT_EN (0x00000080)
90 #define INT_EN_RDFO_INT_EN (0x00000040)
91 #define INT_EN_RSFF_INT_EN (0x00000010)
92 #define INT_EN_RSFL_INT_EN (0x00000008)
93 #define INT_EN_GPIO2_EN (0x00000004)
94 #define INT_EN_GPIO1_EN (0x00000002)
95 #define INT_EN_GPIO0_EN (0x00000001)
96 
97 #define BYTE_TEST (uint16_t)(0x64)
98 #define BYTE_TEST_VAL (0x87654321)
99 
100 #define FIFO_INT (uint16_t)(0x68)
101 #define FIFO_INT_TDAL_MSK (0xFF000000)
102 #define FIFO_INT_TSL_MSK (0x00FF0000)
103 #define FIFO_INT_RSL_MSK (0x000000FF)
104 
105 #define RX_CFG (uint16_t)(0x6C)
106 #define RX_CFG_END_ALIGN4 (0x00000000)
107 #define RX_CFG_END_ALIGN16 (0x40000000)
108 #define RX_CFG_END_ALIGN32 (0x80000000)
109 #define RX_CFG_FORCE_DISCARD (0x00008000)
110 #define RX_CFG_RXDOFF_MSK (0x00003C00)
111 
112 #define TX_CFG (uint16_t)(0x70)
113 #define TX_CFG_TXS_DUMP (0x00008000)
114 #define TX_CFG_TXD_DUMP (0x00004000)
115 #define TX_CFG_TXSAO (0x00000004)
116 #define TX_CFG_TX_ON (0x00000002)
117 #define TX_CFG_STOP_TX (0x00000001)
118 
119 #define HW_CFG (uint16_t)(0x74)
120 #define HW_CFG_MBO (0x00100000)
121 #define HW_CFG_TX_FIF_SZ_MSK (0x000F0000)
122 #define HW_CFG_BITMD_MSK (0x00000004)
123 #define HW_CFG_BITMD_32 (0x00000004)
124 #define HW_CFG_SRST_TO (0x00000002)
125 #define HW_CFG_SRST (0x00000001)
126 
127 #define RX_DP_CTL (uint16_t)(0x78)
128 #define RX_DP_FFWD (0x80000000)
129 
130 #define RX_FIFO_INF (uint16_t)(0x7C)
131 #define RX_FIFO_RXSUSED_MSK (0x00FF0000)
132 #define RX_FIFO_RXDUSED_MSK (0x0000FFFF)
133 
134 #define TX_FIFO_INF (uint16_t)(0x80)
135 #define TX_FIFO_TXSUSED_MSK (0x00FF0000)
136 #define TX_FIFO_TDFREE_MSK (0x0000FFFF)
137 
138 #define PWR_MGMT (uint16_t)(0x84)
139 #define PWR_MGMT_PM_MODE_MSK (0x00003000)
140 #define PWR_MGMT_PM_MODE_MSK_LE (0x00000003)
141 #define PWR_MGMT_PM__D0 (0x00000000)
142 #define PWR_MGMT_PM__D1 (0x00010000)
143 #define PWR_MGMT_PM__D2 (0x00020000)
144 #define PWR_MGMT_PHY_RST (0x00000400)
145 #define PWR_MGMT_WOL_EN (0x00000200)
146 #define PWR_MGMT_ED_EN (0x00000100)
147 #define PWR_MGMT_PME_TYPE_PUPU (0x00000040)
148 #define PWR_MGMT_WUPS_MSK (0x00000030)
149 #define PWR_MGMT_WUPS_NOWU (0x00000000)
150 #define PWR_MGMT_WUPS_D2D0 (0x00000010)
151 #define PWR_MGMT_WUPS_D1D0 (0x00000020)
152 #define PWR_MGMT_WUPS_UNDEF (0x00000030)
153 #define PWR_MGMT_PME_IND_PUL (0x00000008)
154 #define PWR_MGMT_PME_POL_HIGH (0x00000004)
155 #define PWR_MGMT_PME_EN (0x00000002)
156 #define PWR_MGMT_PME_READY (0x00000001)
157 
158 #define GPIO_CFG (uint16_t)(0x88)
159 #define GPIO_CFG_LEDx_MSK (0x70000000)
160 #define GPIO_CFG_LED1_EN (0x10000000)
161 #define GPIO_CFG_LED2_EN (0x20000000)
162 #define GPIO_CFG_LED3_EN (0x40000000)
163 #define GPIO_CFG_GPIOBUFn_MSK (0x00070000)
164 #define GPIO_CFG_GPIOBUF0_PUPU (0x00010000)
165 #define GPIO_CFG_GPIOBUF1_PUPU (0x00020000)
166 #define GPIO_CFG_GPIOBUF2_PUPU (0x00040000)
167 #define GPIO_CFG_GPDIRn_MSK (0x00000700)
168 #define GPIO_CFG_GPIOBUF0_OUT (0x00000100)
169 #define GPIO_CFG_GPIOBUF1_OUT (0x00000200)
170 #define GPIO_CFG_GPIOBUF2_OUT (0x00000400)
171 #define GPIO_CFG_GPIOD_MSK (0x00000007)
172 #define GPIO_CFG_GPIOD0 (0x00000001)
173 #define GPIO_CFG_GPIOD1 (0x00000002)
174 #define GPIO_CFG_GPIOD2 (0x00000004)
175 
176 #define GPT_CFG (uint16_t)(0x8C)
177 #define GPT_CFG_TIMER_EN (0x20000000)
178 #define GPT_CFG_GPT_LOAD_MSK (0x0000FFFF)
179 
180 #define GPT_CNT (uint16_t)(0x90)
181 #define GPT_CNT_MSK (0x0000FFFF)
182 
183 #define FPGA_REV (uint16_t)(0x94)
184 
185 #define ENDIAN (uint16_t)(0x98)
186 #define ENDIAN_BIG (0xFFFFFFFF)
187 
188 #define FREE_RUN (uint16_t)(0x9C)
189 #define FREE_RUN_FR_CNT_MSK (0xFFFFFFFF)
190 
191 #define RX_DROP (uint16_t)(0xA0)
192 #define RX_DROP_RX_DFC_MSK (0xFFFFFFFF)
193 
194 #define MAC_CSR_CMD (uint16_t)(0xA4)
195 #define MAC_CSR_CMD_CSR_BUSY (0x80000000)
196 #define MAC_CSR_CMD_RNW (0x40000000)
197 #define MAC_RD_CMD(Reg) ((Reg & 0x000000FF) | \
198  (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW))
199 #define MAC_WR_CMD(Reg) ((Reg & 0x000000FF) | \
200  (MAC_CSR_CMD_CSR_BUSY))
201 
202 #define MAC_CSR_DATA (uint16_t)(0xA8)
203 
204 #define AFC_CFG (uint16_t)(0xAC)
205 #define AFC_CFG_AFC_HI_MSK (0x00FF0000)
206 #define AFC_CFG_AFC_LO_MSK (0x0000FF00)
207 
208 #define E2P_CMD (uint16_t)(0xB0)
209 #define E2P_DATA (uint16_t)(0xB4)
210 
212 /**** MAC CONTROL/STATUS REGISTERS (accessed through MAC_CSR_CMD/_DATA registers) ****/
217 #define MAC_CR (uint16_t)(0x01)
219 #define MAC_CR_RXALL (0x80000000)
220 #define MAC_CR_HBDIS (0x10000000)
221 #define MAC_CR_RCVOWN (0x00800000)
222 #define MAC_CR_LOOPBK (0x00200000)
223 #define MAC_CR_FDPX (0x00100000)
224 #define MAC_CR_MCPAS (0x00080000)
225 #define MAC_CR_PRMS (0x00040000)
226 #define MAC_CR_INVFILT (0x00020000)
227 #define MAC_CR_PASSBAD (0x00010000)
228 #define MAC_CR_HFILT (0x00008000)
229 #define MAC_CR_HPFILT (0x00002000)
230 #define MAC_CR_LCOLL (0x00001000)
231 #define MAC_CR_BCAST (0x00000800)
232 #define MAC_CR_DISRTY (0x00000400)
233 #define MAC_CR_PADSTR (0x00000100)
234 #define MAC_CR_BOLMT_MSK (0x000000C0)
235 #define MAC_CR_BOLMT_10 (0x00000000)
236 #define MAC_CR_BOLMT_8 (0x00000040)
237 #define MAC_CR_BOLMT_4 (0x00000080)
238 #define MAC_CR_BOLMT_1 (0x000000C0)
239 #define MAC_CR_DFCHK (0x00000020)
240 #define MAC_CR_TXEN (0x00000008)
241 #define MAC_CR_RXEN (0x00000004)
242 
243 #define MAC_ADDRH (uint16_t)(0x02)
244 #define MAC_ADDRH_MSK (0x0000FFFF)
245 
246 #define MAC_ADDRL (uint16_t)(0x03)
247 #define MAC_ADDRL_MSK (0xFFFFFFFF)
248 
249 #define MAC_HASHH (uint16_t)(0x04)
250 #define MAC_HASHH_MSK (0xFFFFFFFF)
251 
252 #define MAC_HASHL (uint16_t)(0x05)
253 #define MAC_HASHL_MSK (0xFFFFFFFF)
254 
255 #define MAC_MIIACC (uint16_t)(0x06)
256 #define MAC_MIIACC_MII_WRITE (0x00000002)
257 #define MAC_MIIACC_MII_BUSY (0x00000001)
258 #define MAC_MII_RD_CMD(Addr,Reg) (((Addr & 0x1f) << 11) | \
259  ((Reg & 0x1f)) << 6)
260 #define MAC_MII_WR_CMD(Addr,Reg) (((Addr & 0x1f) << 11) | \
261  ((Reg & 0x1f) << 6) | \
262  MAC_MIIACC_MII_WRITE)
263 
264 #define MAC_MIIDATA (uint16_t)(0x07)
265 #define MAC_MIIDATA_MSK (0x0000FFFF)
266 #define MAC_MII_DATA(Data) (Data & MAC_MIIDATA_MSK)
267 
268 #define MAC_FLOW (uint16_t)(0x08)
269 #define MAC_FLOW_FCPT_MSK (0xFFFF0000)
270 #define MAC_FLOW_FCPASS (0x00000004)
271 #define MAC_FLOW_FCEN (0x00000002)
272 #define MAC_FLOW_FCBSY (0x00000001)
273 
274 #define MAC_VLAN1 (uint16_t)(0x09)
275 #define MAC_VLAN2 (uint16_t)(0x0A)
276 #define MAC_WUFF (uint16_t)(0x0B)
277 
278 #define MAC_WUCSR (uint16_t)(0x0C)
279 #define MAC_WUCSR_GUE (0x00000200)
280 #define MAC_WUCSR_WUFR (0x00000040)
281 #define MAC_WUCSR_MPR (0x00000020)
282 #define MAC_WUCSR_WUEN (0x00000004)
283 #define MAC_WUCSR_MPEN (0x00000002)
284 
285 #define MAC_COE_CR (uint16_t)(0x0D)
286 #define MAC_COE_CR_TXCOE_EN (0x00010000)
287 #define MAC_COE_CR_RXCOE_MODE (0x00000002)
288 #define MAC_COE_CR_RXCOE_EN (0x00000001)
289 
292 /**** PHY CONTROL/STATUS REGISTERS (accessed through MAC_MIIACC/_MIIDATA registers) ****/
297 #define PHY_BCR (uint16_t)(0x00)
299 #define PHY_BCR_RST (0x8000)
300 #define PHY_BCR_LOOPBK (0x4000)
301 #define PHY_BCR_SS (0x2000)
302 #define PHY_BCR_ANE (0x1000)
303 #define PHY_BCR_PWRDN (0x0800)
304 #define PHY_BCR_RSTAN (0x0200)
305 #define PHY_BCR_FDPLX (0x0100)
306 #define PHY_BCR_COLLTST (0x0080)
307 
308 #define PHY_BSR (uint16_t)(0x01)
309 #define PHY_BSR_100_T4_ABLE (0x8000)
310 #define PHY_BSR_100_TX_FDPLX (0x4000)
311 #define PHY_BSR_100_TX_HDPLX (0x2000)
312 #define PHY_BSR_10_FDPLX (0x1000)
313 #define PHY_BSR_10_HDPLX (0x0800)
314 #define PHY_BSR_ANC (0x0020)
315 #define PHY_BSR_REM_FAULT (0x0010)
316 #define PHY_BSR_AN_ABLE (0x0008)
317 #define PHY_BSR_LINK_STATUS (0x0004)
318 #define PHY_BSR_JAB_DET (0x0002)
319 #define PHY_BSR_EXT_CAP (0x0001)
320 
321 #define PHY_ID1 (uint16_t)(0x02)
322 #define PHY_ID1_MSK (0xFFFF)
323 #define PHY_ID1_LAN9118 (0x0007)
324 #define PHY_ID1_LAN9218 (PHY_ID1_LAN9118)
325 
326 #define PHY_ID2 (uint16_t)(0x03)
327 #define PHY_ID2_MSK (0xFFFF)
328 #define PHY_ID2_MODEL_MSK (0x03F0)
329 #define PHY_ID2_REV_MSK (0x000F)
330 #define PHY_ID2_LAN9118 (0xC0D1)
331 #define PHY_ID2_LAN9218 (0xC0C3)
332 
333 #define PHY_ANAR (uint16_t)(0x04)
334 #define PHY_ANAR_NXTPG_CAP (0x8000)
335 #define PHY_ANAR_REM_FAULT (0x2000)
336 #define PHY_ANAR_PAUSE_OP_MSK (0x0C00)
337 #define PHY_ANAR_PAUSE_OP_NONE (0x0000)
338 #define PHY_ANAR_PAUSE_OP_ASLP (0x0400)
339 #define PHY_ANAR_PAUSE_OP_SLP (0x0800)
340 #define PHY_ANAR_PAUSE_OP_BOTH (0x0C00)
341 #define PHY_ANAR_100_T4_ABLE (0x0200)
342 #define PHY_ANAR_100_TX_FDPLX (0x0100)
343 #define PHY_ANAR_100_TX_ABLE (0x0080)
344 #define PHY_ANAR_10_FDPLX (0x0040)
345 #define PHY_ANAR_10_ABLE (0x0020)
346 
347 #define PHY_ANLPAR (uint16_t)(0x05)
348 #define PHY_ANLPAR_NXTPG_CAP (0x8000)
349 #define PHY_ANLPAR_ACK (0x4000)
350 #define PHY_ANLPAR_REM_FAULT (0x2000)
351 #define PHY_ANLPAR_PAUSE_CAP (0x0400)
352 #define PHY_ANLPAR_100_T4_ABLE (0x0200)
353 #define PHY_ANLPAR_100_TX_FDPLX (0x0100)
354 #define PHY_ANLPAR_100_TX_ABLE (0x0080)
355 #define PHY_ANLPAR_10_FDPLX (0x0040)
356 #define PHY_ANLPAR_10_ABLE (0x0020)
357 
358 #define PHY_ANEXPR (uint16_t)(0x06)
359 #define PHY_ANEXPR_PARDET_FAULT (0x0010)
360 #define PHY_ANEXPR_LP_NXTPG_CAP (0x0008)
361 #define PHY_ANEXPR_NXTPG_CAP (0x0004)
362 #define PHY_ANEXPR_NEWPG_REC (0x0002)
363 #define PHY_ANEXPR_LP_AN_ABLE (0x0001)
364 
365 #define PHY_MCSR (uint16_t)(0x11)
366 #define PHY_MCSR_EDPWRDOWN (0x2000)
367 #define PHY_MCSR_ENERGYON (0x0002)
368 
369 #define PHY_SPMODES (uint16_t)(0x12)
370 
371 #define PHY_CSIR (uint16_t)(0x1B)
372 #define PHY_CSIR_SQEOFF (0x0800)
373 #define PHY_CSIR_FEFIEN (0x0020)
374 #define PHY_CSIR_XPOL (0x0010)
375 
376 #define PHY_ISR (uint16_t)(0x1D)
377 #define PHY_ISR_INT7 (0x0080)
378 #define PHY_ISR_INT6 (0x0040)
379 #define PHY_ISR_INT5 (0x0020)
380 #define PHY_ISR_INT4 (0x0010)
381 #define PHY_ISR_INT3 (0x0008)
382 #define PHY_ISR_INT2 (0x0004)
383 #define PHY_ISR_INT1 (0x0002)
384 
385 #define PHY_IMR (uint16_t)(0x1E)
386 #define PHY_IMR_INT7 (0x0080)
387 #define PHY_IMR_INT6 (0x0040)
388 #define PHY_IMR_INT5 (0x0020)
389 #define PHY_IMR_INT4 (0x0010)
390 #define PHY_IMR_INT3 (0x0008)
391 #define PHY_IMR_INT2 (0x0004)
392 #define PHY_IMR_INT1 (0x0002)
393 
394 #define PHY_PHYSCSR (uint16_t)(0x1F)
395 #define PHY_PHYSCSR_ANDONE (0x1000)
396 #define PHY_PHYSCSR_4B5B_EN (0x0040)
397 #define PHY_PHYSCSR_SPEED_MSK (0x001C)
398 #define PHY_PHYSCSR_SPEED_10HD (0x0004)
399 #define PHY_PHYSCSR_SPEED_10FD (0x0014)
400 #define PHY_PHYSCSR_SPEED_100HD (0x0008)
401 #define PHY_PHYSCSR_SPEED_100FD (0x0018)
402 
405 typedef struct {
406  uint32_t ID_REV_REG;
407  uint32_t IRQ_CFG_REG;
408  uint32_t INT_STS_REG;
409  uint32_t INT_EN_REG;
410  uint32_t BYTE_TEST_REG;
411  uint32_t FIFO_INT_REG;
412  uint32_t RX_CFG_REG;
413  uint32_t TX_CFG_REG;
414  uint32_t HW_CFG_REG;
415  uint32_t RX_DP_CTL_REG;
416  uint32_t RX_FIFO_INF_REG;
417  uint32_t TX_FIFO_INF_REG;
418  uint32_t PMT_CTRL_REG;
419  uint32_t GPIO_CFG_REG;
420  uint32_t GPT_CFG_REG;
421  uint32_t GPT_CNT_REG;
422  uint32_t WORD_SWAP_REG;
423  uint32_t FREE_RUN_REG;
424  uint32_t RX_DROP_REG;
425  uint32_t MAC_CSR_CMD_REG;
426  uint32_t MAC_CSR_DATA_REG;
427  uint32_t AFC_CFG_REG;
428  uint32_t E2P_CMD_REG;
429  uint32_t E2P_DATA_REG;
430 } CSR_regs;
431 
432 CSR_regs regs;
433 
434 // FUNCTION PROTOTYPES
439 uint8_t lan9211_init();
446 void GetMAC_Reg(uint8_t idx, uint32_t *data);
453 void SetMAC_Reg(uint8_t idx, uint32_t data);
460 void GetPHY_Reg(uint8_t idx, uint32_t *data);
467 void SetPHY_Reg(uint8_t idx, uint32_t data);
474 void lan9211_CSR_read(uint16_t lan9211_reg, uint32_t *data);
481 void lan9211_CSR_write(uint16_t lan9211_reg, uint32_t data);
488 int lan9211_receiveFrame(uint8_t *buffer);
494 int lan9211_sendFrame(const uint8_t *frame, uint16_t length);
499 void CSR_regsDump();
500 
501 #endif //SMSC9211_H
lan9211_sendFrame
int lan9211_sendFrame(const uint8_t *frame, uint16_t length)
This Function is used to send an Ethernet frame.
Definition: lan9211.c:384
lan9211_init
uint8_t lan9211_init()
This Function initializes the LAN9211 controller with a default configuration.
Definition: lan9211.c:102
GetMAC_Reg
void GetMAC_Reg(uint8_t idx, uint32_t *data)
This Function is used to read an internal register of the MAC.
Definition: lan9211.c:24
lan9211_CSR_write
void lan9211_CSR_write(uint16_t lan9211_reg, uint32_t data)
This Function is used to read a value into a CSR (Control and Status Register) of the LAN9211.
Definition: lan9211.c:437
CSR_regs
Definition: lan9211.h:404
CSR_regsDump
void CSR_regsDump()
This Function stores all the PIO register's values into the 'regs' struct variable.
Definition: lan9211.c:443
SetPHY_Reg
void SetPHY_Reg(uint8_t idx, uint32_t data)
This Function is used to write an internal register of the PHY.
Definition: lan9211.c:86
lan9211_CSR_read
void lan9211_CSR_read(uint16_t lan9211_reg, uint32_t *data)
This Function is used to write a value into a CSR (Control and Status Register) of the LAN9211.
Definition: lan9211.c:431
GetPHY_Reg
void GetPHY_Reg(uint8_t idx, uint32_t *data)
This Function is used to read an internal register of the PHY.
Definition: lan9211.c:68
SetMAC_Reg
void SetMAC_Reg(uint8_t idx, uint32_t data)
This Function is used to write an internal register of the MAC.
Definition: lan9211.c:46
lan9211_receiveFrame
int lan9211_receiveFrame(uint8_t *buffer)
This Function is used to receive an Ethernet frame.
Definition: lan9211.c:300