|
#define | PHY_BCR (uint16_t)(0x00) |
|
#define | PHY_BCR_RST (0x8000) |
|
#define | PHY_BCR_LOOPBK (0x4000) |
|
#define | PHY_BCR_SS (0x2000) |
|
#define | PHY_BCR_ANE (0x1000) |
|
#define | PHY_BCR_PWRDN (0x0800) |
|
#define | PHY_BCR_RSTAN (0x0200) |
|
#define | PHY_BCR_FDPLX (0x0100) |
|
#define | PHY_BCR_COLLTST (0x0080) |
|
#define | PHY_BSR (uint16_t)(0x01) |
|
#define | PHY_BSR_100_T4_ABLE (0x8000) |
|
#define | PHY_BSR_100_TX_FDPLX (0x4000) |
|
#define | PHY_BSR_100_TX_HDPLX (0x2000) |
|
#define | PHY_BSR_10_FDPLX (0x1000) |
|
#define | PHY_BSR_10_HDPLX (0x0800) |
|
#define | PHY_BSR_ANC (0x0020) |
|
#define | PHY_BSR_REM_FAULT (0x0010) |
|
#define | PHY_BSR_AN_ABLE (0x0008) |
|
#define | PHY_BSR_LINK_STATUS (0x0004) |
|
#define | PHY_BSR_JAB_DET (0x0002) |
|
#define | PHY_BSR_EXT_CAP (0x0001) |
|
#define | PHY_ID1 (uint16_t)(0x02) |
|
#define | PHY_ID1_MSK (0xFFFF) |
|
#define | PHY_ID1_LAN9118 (0x0007) |
|
#define | PHY_ID1_LAN9218 (PHY_ID1_LAN9118) |
|
#define | PHY_ID2 (uint16_t)(0x03) |
|
#define | PHY_ID2_MSK (0xFFFF) |
|
#define | PHY_ID2_MODEL_MSK (0x03F0) |
|
#define | PHY_ID2_REV_MSK (0x000F) |
|
#define | PHY_ID2_LAN9118 (0xC0D1) |
|
#define | PHY_ID2_LAN9218 (0xC0C3) |
|
#define | PHY_ANAR (uint16_t)(0x04) |
|
#define | PHY_ANAR_NXTPG_CAP (0x8000) |
|
#define | PHY_ANAR_REM_FAULT (0x2000) |
|
#define | PHY_ANAR_PAUSE_OP_MSK (0x0C00) |
|
#define | PHY_ANAR_PAUSE_OP_NONE (0x0000) |
|
#define | PHY_ANAR_PAUSE_OP_ASLP (0x0400) |
|
#define | PHY_ANAR_PAUSE_OP_SLP (0x0800) |
|
#define | PHY_ANAR_PAUSE_OP_BOTH (0x0C00) |
|
#define | PHY_ANAR_100_T4_ABLE (0x0200) |
|
#define | PHY_ANAR_100_TX_FDPLX (0x0100) |
|
#define | PHY_ANAR_100_TX_ABLE (0x0080) |
|
#define | PHY_ANAR_10_FDPLX (0x0040) |
|
#define | PHY_ANAR_10_ABLE (0x0020) |
|
#define | PHY_ANLPAR (uint16_t)(0x05) |
|
#define | PHY_ANLPAR_NXTPG_CAP (0x8000) |
|
#define | PHY_ANLPAR_ACK (0x4000) |
|
#define | PHY_ANLPAR_REM_FAULT (0x2000) |
|
#define | PHY_ANLPAR_PAUSE_CAP (0x0400) |
|
#define | PHY_ANLPAR_100_T4_ABLE (0x0200) |
|
#define | PHY_ANLPAR_100_TX_FDPLX (0x0100) |
|
#define | PHY_ANLPAR_100_TX_ABLE (0x0080) |
|
#define | PHY_ANLPAR_10_FDPLX (0x0040) |
|
#define | PHY_ANLPAR_10_ABLE (0x0020) |
|
#define | PHY_ANEXPR (uint16_t)(0x06) |
|
#define | PHY_ANEXPR_PARDET_FAULT (0x0010) |
|
#define | PHY_ANEXPR_LP_NXTPG_CAP (0x0008) |
|
#define | PHY_ANEXPR_NXTPG_CAP (0x0004) |
|
#define | PHY_ANEXPR_NEWPG_REC (0x0002) |
|
#define | PHY_ANEXPR_LP_AN_ABLE (0x0001) |
|
#define | PHY_MCSR (uint16_t)(0x11) |
|
#define | PHY_MCSR_EDPWRDOWN (0x2000) |
|
#define | PHY_MCSR_ENERGYON (0x0002) |
|
#define | PHY_SPMODES (uint16_t)(0x12) |
|
#define | PHY_CSIR (uint16_t)(0x1B) |
|
#define | PHY_CSIR_SQEOFF (0x0800) |
|
#define | PHY_CSIR_FEFIEN (0x0020) |
|
#define | PHY_CSIR_XPOL (0x0010) |
|
#define | PHY_ISR (uint16_t)(0x1D) |
|
#define | PHY_ISR_INT7 (0x0080) |
|
#define | PHY_ISR_INT6 (0x0040) |
|
#define | PHY_ISR_INT5 (0x0020) |
|
#define | PHY_ISR_INT4 (0x0010) |
|
#define | PHY_ISR_INT3 (0x0008) |
|
#define | PHY_ISR_INT2 (0x0004) |
|
#define | PHY_ISR_INT1 (0x0002) |
|
#define | PHY_IMR (uint16_t)(0x1E) |
|
#define | PHY_IMR_INT7 (0x0080) |
|
#define | PHY_IMR_INT6 (0x0040) |
|
#define | PHY_IMR_INT5 (0x0020) |
|
#define | PHY_IMR_INT4 (0x0010) |
|
#define | PHY_IMR_INT3 (0x0008) |
|
#define | PHY_IMR_INT2 (0x0004) |
|
#define | PHY_IMR_INT1 (0x0002) |
|
#define | PHY_PHYSCSR (uint16_t)(0x1F) |
|
#define | PHY_PHYSCSR_ANDONE (0x1000) |
|
#define | PHY_PHYSCSR_4B5B_EN (0x0040) |
|
#define | PHY_PHYSCSR_SPEED_MSK (0x001C) |
|
#define | PHY_PHYSCSR_SPEED_10HD (0x0004) |
|
#define | PHY_PHYSCSR_SPEED_10FD (0x0014) |
|
#define | PHY_PHYSCSR_SPEED_100HD (0x0008) |
|
#define | PHY_PHYSCSR_SPEED_100FD (0x0018) |
|